1. Field of the Invention
The present invention relates to a system for automatically drawing network charts such as logic diagrams, function diagrams, block diagrams, process drawings, related tree diagrams, and layouts of printed circuit boards, and in particular to a method of and a system for automatically generating network charts whereby logic diagrams, function diagrams, or circuit diagrams are generated on the basis of circuit components such as circuit devices or partial circuits and their connection information.
2. Description of the Related Art
Various methods have heretofore been proposed with regard to automatic logic circuit diagram generation. For example, these methods are disclosed in JP-A-61-204775, Technical Report CAS 84-134 (1984) of The Institute of Electronics and Communication Engineers of Japan, pp. 47-54, JP-A-60-205672, JP-A-60-176177, JP-A-2-075072, and 30th National Convention Record (First Term of 1985) of Information Processing Society of Japan, pp. 1901-1904 and pp. 1973-1974.
In general, automatic logic circuit diagram generation is implemented by determining placement of plotting symbols, such as respective circuit components, by means of automatic placement and thereafter determining wiring between circuit components by means of automatic wiring.
As for the conventional method of placing circuit components on a logic circuit in the automatic logic circuit diagram generation method, positions wherein plotting symbols can be placed are limited to positions of checkers imagined on a drawing, and placement of plotting symbols is successively determined in accordance with wiring relations between plotting symbols, i.e., connection relations between circuit components in a predetermined direction from one end of the drawings to another, such as a direction proceeding from the output side to the input side or a direction proceeding from the input side to the output side. As the procedure for this placement determination, level assignment of plotting symbols, i.e., column assignment (level assignment) for placement is first performed according to the wiring relations with an input terminal, i.e., an input port of each plotting symbol, or an output terminal, i.e., an output port as the starting point. Thereafter, plotting symbols in each column are successively positioned by minimizing intersections of wiring to plotting symbols of a preceding column (level) already positioned or minimizing the total length of all wiring between plotting symbols.
Especially in case a link of consecutive wiring between plotting symbols forms a loop (including a cycle) in the above described level assignment, the loop is disconnected once and then level assignment is performed in general. As this loop disconnection method, (1) a method of defining the position of a predetermined plotting symbol as the disconnection point of that loop, or (2) a method of detecting all loops of a circuit diagram and defining a location where overlap of those loops is maximized as the disconnection point of loops can be used, for example.
However, level assignment of the prior art has the following problems because a loop formed by plotting symbols representing respective circuit components and wiring between those plotting symbols is disconnected.
The above described method (1) wants universality because a loop cannot be disconnected unless a particular plotting symbol such as a flip-flop is included in that loop.
For all loops in the circuit diagram, all paths forming those loops must be detected in the above described method (2). Therefore, the circuit scale becomes large. If the number of loops becomes large, the processing time becomes extensive.
That is to say, a circuit is divided into small portions, and thereafter logic circuit diagrams are automatically generated and loops are disconnected in places of flip-flops. Therefore, the prior art has a problem that universality and processing efficiency are not satisfactorily considered.